Simultaneous Multithreading: Exploiting Instruction-Level and Thread-Level Parallelism in Microprocessors

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Simultaneous Multithreading: Exploiting Instruction-Level and Thread-Level Parallelism in Microprocessors

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dc.contributor.advisor Wonnacott, David G.
dc.contributor.author Butera, Jeffrey
dc.date.accessioned 2011-10-18T19:06:19Z
dc.date.available 2011-10-18T19:06:19Z
dc.date.issued 2011
dc.identifier.uri http://hdl.handle.net/10066/7570
dc.description.abstract Increasing the performance of microprocessors has always been a pressing issue in the fields of Computer Science and Computer Engineering. The first processors functioned by executing a single stream of sequential instructions. The initial approach to increasing the speed of instruction execution involved using smaller and faster transistors so that the clock frequency could be increased. This approach was stymied by slow memory accesses that could not keep up with a fast clock cycle. Cache memories were developed to keep frequently accessed data closer to the processor to prevent the types of stalls. RISC, reduced instruction set computing, architectures were also designed to allow for faster clock cycles and execution. After RISC, the focus shifted away from speeding up the execution of a single instruction and moved towards increasing the number of instructions that can be active in a single clock cycle. Different designs, such as pipelining and superscalars, allowed multiple instructions to be issued in the same clock cycle, but were limited by increased power consumption, heat, and chip size. Multi-core and multiprocessor designs allowed multiple threads of instructions to be simultaneously executed on different processors or cores. These designs were improved by the development of multithreading, which aimed to increase threadlevel parallelism on a single core. This thesis addresses the intricacies of a specific type of hardware multithreading: Simultaneous Multithreading (SMT). SMT is a technique used to increase the performance of a microprocessor by exploiting parallelism in all available forms. SMT combines instruction-level and thread-level parallelism and enables multiple instructions from multiple threads to be issued in the same clock cycle. This paper is a detailed examination of Simultaneous Multithreading and will specifically address: how multiple instructions are fetched and issued simultaneously, how hardware resources are designated amongst threads, the performance upgrade associated with SMT in terms of instructions per cycle, the energy-efficiency of the design, and how SMT is utilized in general purpose microprocessors such as in the Intel Pentium 4 Hyper-Threading processor. en
dc.description.sponsorship Haverford College. Dept. of Computer Science en
dc.language.iso en_US en
dc.rights.uri http://creativecommons.org/licenses/by-nc/3.0/us/
dc.subject.lcsh Simultaneous multithreading processors
dc.subject.lcsh Parallel processing (Electronic computers)
dc.title Simultaneous Multithreading: Exploiting Instruction-Level and Thread-Level Parallelism in Microprocessors en
dc.type Thesis (B.S.) en


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http://creativecommons.org/licenses/by-nc/3.0/us/ Except where otherwise noted, this item's license is described as http://creativecommons.org/licenses/by-nc/3.0/us/