Concurrency in Multi-Core Processor Design

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Title: Concurrency in Multi-Core Processor Design
Author: Clancy, Patrick
Advisor: Wonnacott, David G.
Department: Haverford College. Dept of Computer Science.
Type: Thesis (B.S.)
Running Time: 392439 bytes
Issue Date: 2007
Abstract: It is possible to extend a microprocessor from a single core to a multiple cores by replicating the single core processor, and interfacing them to main memory bus via a bus arbitrator. With a multi-core processor, the possibilities for parallel programs are apparent, but the programmer must overcome those obstacles with lock based programming. Transactional Memory would provide a means for programmers to handle highly concurrent programming in a more forgiving environment. This thesis surveys these topics and discusses possible implementations in terms of the HERA architecture.
Subject: Multiprocessors
Subject: Parallel processing (Electronic computers)
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2007ClancyP.pdf Thesis (Haverford users only) 383.2Kb PDF
Haverford_departmental_permission.pdf **Archive Staff Only** 30.60Kb PDF


Clancy, Patrick. "Concurrency in Multi-Core Processor Design". 2007. Available electronically from

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