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Please use this identifier to cite or link to this item:
http://hdl.handle.net/10066/1487
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| Title: | Concurrency in Multi-Core Processor Design |
| Author(s): | Clancy, Patrick |
| Advisor(s): | Wonnacott, David G. |
| Department: | Haverford College. Dept of Computer Science. |
| Abstract: | It is possible to extend a microprocessor from a single core to a multiple cores by replicating
the single core processor, and interfacing them to main memory bus via a bus arbitrator.
With a multi-core processor, the possibilities for parallel programs are apparent, but the programmer must overcome those obstacles with lock based programming. Transactional Memory would provide a means for programmers to handle highly concurrent programming in a more forgiving environment. This thesis surveys these topics and discusses possible implementations in terms of the HERA architecture. |
| URI: | http://hdl.handle.net/10066/1487 |
| Appears in Collections: | Computer Science
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Files in This Item:
| File |
Description |
Size | Format |
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| 2007ClancyP.pdf | Thesis | 383Kb | Adobe PDF | View/Open |
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